Inseto

Month: December 2019

Semiconductor Photolithography Basics

14th December 2019

Introduction to the basics of semiconductor photolithography (IKB-038).

Semiconductor photolithography at its most general is the process of patterning the surface of a substrate to build up a complex design or structure.

Photo (UV) Lithography

Photo (or UV) lithography is the technique of pattering through the use of a light sensitive polymer (called photoresist) and a stencil (called a photomask). Through a series of chemical treatments this pattern is inscribed by either etching away of exposed areas or the deposition of new material to fabricate the desired device. For the manufacture of complex devices the number of photolithographic cycles increases.

The first step in any photolithographic process is to prepare the substrate – in most cases the substrate is a silicon wafer but can in theory be any material. Substrate preparation is undertaken to improve the adhesion of the photoresist to the substrate. Typical steps include substrate cleaning – to remove any dirt/contaminates, dehydration bake – to remove any water and then the addition of an adhesion promoter. Going through these steps will reduce the number of contaminates – both organic and inorganic – which will ensure the best results as we move through the lithography process.

Lithography Process
Figure 1.
a) Cleaned and prepared substrate
b) Photoresist spun onto substrate
c) Align to photomask and expose to UV light
d) Develop photoresist.
• Positive removes exposed resist
• Negative removes unexposed resist

Once the substrate has been prepared the photoresist can be applied to the surface. To get the best results a thin uniform coating is required. The thickness of this film is of extreme importance and so the manner in which the resist is dispensed must be precisely controlled. A number of methods have been developed to dispense and coat a substrate with photoresist, the most common deployed of these is spin-coating. A summary of these coating methods can also be found on the Inseto Knowledge base.

In spin-coating the photoresist is deposited onto the substrate and the substrate and resist are then spun on a turntable at 1000s of rpm, spreading out the viscous photoresist into a thin layer. This thin resist is then soft-baked on a hotplate to remove excess solvent and to stabilise the resist film.

The next step in the photolithography process is to align the resist-covered substrate to the photomask and to expose it to UV light. The critical principle in photolithography is that the solubility of the photoresist is changed once exposed to UV light. How this solubility changes defines the type of photoresist – either positive or negative – and the details of the manufacturing process that should be used.

Photoresists come in two categories: positive or negative. In a positive resist, the part of the film that is exposed to the resist becomes more soluble and can be removed with a developer. In a negative the opposite happens, where the resist has been exposed to light the resist becomes harder and can’t be removed by the developer. There are many different compositions and versions of resist, allowing for different heights, temperatures, exposure settings and structures to be manufactured.

When aligning the substrate to the mask we use a mask aligner or a stepper to control where the pattern on the mask is projected onto the substrate below. A mask aligner is a faster process, taking a pattern the same size as the wafer and projecting it onto the wafer. A stepper takes a small pattern and exposes that onto the wafer before moving the substrate a short distance and exposing the same pattern onto a different part of the wafer – replicating the same pattern over and over again.

The crucial aspect of the align and expose step is the exposure of the photoresist with UV light. The UV source can either be a traditional broadband mercury light or the more recent advance using a UV LED array.  The UV source defines the resolution (smallest features) of the lithography process. A rough rule of thumb is that the resolution achievable is slightly more than half the wavelength of light. UV light has a wavelength of ~465nm, so the resolution achieved will be ~250 nm. There are a number of exposure modes available which will also affect the resolution achievable.

Once exposed, the next step is to develop the resist. The developer will wash away either the exposed or unexposed parts of the resist film, depending on the nature of the photoresist. Development is either done as a spray, where a fine mist of developer is sprayed onto the exposed substrate or as a puddle, where a pool of developer is poured onto the exposed substrate. In both cases it will remove the unwanted photoresist leaving the desired pattern.

Now the substrate is ready for the next step of the processing, either the deposition of a thin film onto the surface of the substrate or the etching and removal of the substrate. These techniques can be combined together with multiple iterations of photolithography to make complex designs and patterns.

Other microfabrication techniques similar to lithography such as imprint lithography or electron-beam lithography can also be incorporated into the manufacturing process to produce devices with increasing complexity and functionality.

For further information on our range of equipment for UV Lithography, please click HERE

Author

Date

Version

Author

Chris Valentine

Date

25 October 2019

Version

IKB038 Rev. 2

Download

Semiconductor Wafer Selection Guide

14th December 2019

A guide to semiconductor wafer selection, explaining the meaning of the various parameters in our wafer nomenclature charts (IKB-046).

Silicon Wafers

Semiconductor wafer selection: Silicon wafers are a thin slice of semiconducting material that is widely used in the production of electronic and micromechanical devices. They are characterised by a number of parameters, which affect their suitability and performance for a chosen task.

1. Wafer diameter

Diameter of the wafer listed in mm. Typically wafers are talked about in inches; typical sizes are 2”,3”,4”,5”,6”,8”& 12” – with 4”,6” and 8” the most commonly used in industry and academia.

2. Type

Type refers to the electrical behaviour of the wafer. Intrinsic (I), behaves as pure silicon. N-type, dominant charge carriers are electrons. P-type, dominant charge carriers are holes. Whether a wafer is P-type or N-type will affect the electrical response of  any device manufactured.

3. Crystallographic Orientation

Wafers are grown as single crystals that have an ordered, regular and repeating structure.  When they are sliced from the ingot the flat surface is aligned along one of several relative directions, known as the orientation. The orientation is classified by Miller indices, typical indices being (100), (110) and (111). Orientation affects the physical properties of the silicon wafer – how it is etched, ion implantation and how it integrates with other materials.

4. Dopant

The dopant is a material that has been deliberately implanted in the silicon to change the TYPE of the silicon. TYPE and DOPANT are linked.

Typical N-type dopants are Phosphorus, Arsenic, and Antimony. These all provide an extra electron to the silicon which is then free to carry current.

Typical P-type dopants are Boron & Gallium. These have one less electron and so leave a ‘hole’ in the silicon lattice which is free to carry current.

5. Growth Method

The growth method refers to the process by which the silicon ingot is grown. There are two main techniques: Czochralski Zone (CZ) and Float Zone (FZ).

CZ: This is the dominant method used to grow commercial silicon wafers due to the better resistance to thermal stress, speed of production and low cost. CZ involves the heating a crucible of polycrystalline silicon until it melts; then dipping a seed of single crystal silicon in and withdrawing slowly to produce an ingot of crystalline silicon.

FZ: This is a high purity alternative to the CZ method. A polycrystalline rod of silicon and a single crystal seed are held face to face and rotated. The rod is then heated by a thin ring and the seed brought in to contact with the tip. The molten silicon orders itself into the single crystal and the heating zone is slowly moved up to extend the ingot of silicon. FZ produces higher purity and higher resistivity Si than is typically possible in CZ processes.

6. Grade

Grade refers to the variety in the quality of the wafers. Typically these are PRIME, TEST and RECLAIMED.

  • Prime are the highest quality and produced to the highest tolerances on flatness, cleanliness and polish
  • Test are similar to prime, except with less rigorous specifications to flatness and cleanliness.
  • Reclaimed are wafers that have been stripped and polished of any previous patterning or processing.

There are sometimes other grades of Si wafer mentioned but these are either synonyms of the above or have a specific tolerance on a certain parameter.

7. Material

The material is the bulk material of the wafer, typically silicon, but this may vary – some transparent substrates such as glass or quartz are needed for optical devices, and more exotic compound materials such as GaAs or InP for specific band gaps.

8. Resistivity

Resistivity is the measure of the resistance to current flow and the movement of the charge carriers (either holes or electrons) through the silicon. Resistivity is measured in Ohm-cm. The dopant level can be adjusted to reach target resistivity’s, with higher doping lowering the resistivity.

9. Thickness

The thickness of the silicon wafer affects the mechanical properties and is typically expressed in µm (microns) and with a tolerance (± 20µm), The tolerance is measured through a total thickness variation (TTV).

10. Polish

Wafer polishing is the final step in the manufacture of silicon wafers, which allows the production of a smooth, super-flat mirrored surface. There are two options for polishing: single side polish (SSP) and double side polish (DSP)

SSP: Only one face is polished, the second (the backside) is etched.

DSP: Both faces are polished, giving a high flatness to the wafer.

11. Alignment Fiducial

Alignment fiducial refers to the flats or notches used to identify the wafer. Originally flats were used to identify TYPE and well as ORIENTATION, but now there is less convention about what the flats mean, and notches are quite common on 8” (200mm) wafers.

12. Other

At Inseto, we use “Other” to indicate if the wafers are laser marked with a unique identifier or if they have been stacked in a particular manner.

Silicon Wafers and a guide to the key material selection properties.

Coated Wafers

Semiconductor wafer selection: Coated wafers are a subset of silicon wafers where either one or both surfaces have been coated with an additional material. In the Inseto naming convention they are characterised by COATING – the material the wafer is coated with; and COATING THICKNESS – the thickness of that coating, typically µm, nm or Å.

a. Oxide wafers

One typical coating requested is an Oxide coating. This can be a thermal oxide coating (ATOx) which always coats both sides of the wafer. ATOx stands for atmospheric thermal oxide. Other oxide coating methods include:

Dry Oxide – which produces a thinner oxide layer but with a higher uniformity film.

PECVD Oxide – produces a coating on a single side of the wafer

b. Nitride wafers

A second typical coating requested is a Nitride coating. Silicon Nitride (SiN) offers different mechanical and chemical properties to oxide layers. The nitride can be deposited by PECVD, LPCVD or low stress LPCVD. These variants are changes in the method of deposition and alter the final physical and mechanical properties of the film.

Oxide Coated Silicon Wafers and a guide to the key material selection properties.

Glass Wafers

Glass wafers are generally used where the substrate is required to be transparent. At Inseto we separate out these from silicon and coated silicon wafers as they have some distinct parameters which inform your selection.

1. Wafer diameter

As with Silicon wafers, the diameter is typically listed in mm but may be referred to in inches. 

2. Material

This lists the material the glass is made from, typical options include Borosilicate, Fused Quartz, Fused Silica and Crystal Quartz. Some people use these terms interchangeably or will drop the ‘fused’ and ‘crystal’ terms

3. Crystallographic Orientation

Fused Quartz and Fused Silica have no orientation as they are not crystalline materials. Crystal quartz however does and can be X-Cut, Y-Cut, AT-Cut and ST-Cut depending on how the wafer is removed from the larger crystal.

4. Grade

The grade of the glass wafer listed here refers to the manufacturers specifications. Each has its own specific chemical, mechanical and optical properties.

5. Thickness

As with Silicon wafers this refers to the thickness and tolerance of the wafer, typically listed in µm.

6. Polish

As with Silicon wafers this refers to the finish on the surface of the glass and can be either SSP or DSP. Alongside this there is a rating X/Y, where both X and Y are numbers. X refers to the width of a scratch in µm and Y the diameter of a dig, pit or bubble in hundreths of a mm.

7. Edge Shape

This denotes how the edge of the glass wafer has been shaped. Most commonly a C shape, but chamfered and square cut are also options.

8. Alignment fiducial, Coating type, Coating thickness

The final 3 parameters we list are alignment fiducial, coating type and coating thickness and contain the same information as in the Silicon wafers.

Silica Wafers for Semiconductor Research and a guide to the key material selection properties.

SOI Wafers

Semiconductor wafer selection: The fourth wafer type we separate out is SOI (Silicon on Insulator). SOI wafers make use of a silicon – insulator – silicon substrate and are used for specific applications where reducing parasitic capacitance in the device is crucial. Many photonics devices are also made using SOI wafers to fabricate thin Si optical channels, integrated heaters and other optical devices. They are also used in MEMS production where the thin Si layer is patterned and etched and the underlying insulator layer removed by selective etching to leave a free standing feature. These applications include strain gauges, resonant cantilevers for AFM and molecular scale manipulators as well as microfluidic devices. The choice of insulator within the silicon sandwich is highly specific to the application, but silicon dioxide and sapphire are typical choices for microelectronics and radio frequency applications respectively.  The top layer of silicon is referred to as the ‘device’, the bottom layer the ‘handle’.

There are some standard parameters listed as with silicon wafers – these are Diameter, Type and Crystallographic Orientation. We then list the parameters specific to SOI wafers.

1. Device Thickness

This is the thickness of the top layer of silicon, typically in µm.

2. Growth Method

This is listed twice in an SOI wafer. First is the growth method of the device layer and can be CZ or FZ.

3. Device Resistivity

Measured as with a standard silicon wafer, this is the resistivity of the top layer of silicon in Ohm-cm.

4. BOx

This is the thickness of the insulator layer or ‘buried oxide’ layer, hence BOx.  As with all thicknesses typically µm but can be nm or Å.    

5. Handle Thickness

The thickness of the bottom layer of silicon, typically in µm.

6. Growth Method

This second listing of growth method relates to the handle layer of silicon.

7. Handle Resistivity

Measured as with a standard silicon wafer, this is the resistivity of the bottom layer of silicon in Ohm-cm

8. Backside

This relates to how the backside of the handle layer has been treated and can be a variety of finishes including: Polished, etched, oxide, no oxide and laser marked.

SOI Wafers material selection properties

SOS Wafers

Semiconductor wafer selection: Another type of wafer is SOS (Silicon on Sapphire). SOS wafers make use of a silicon layer grown on a sapphire substrate and are a specific subset of SOI wafers, where the insulator is sapphire. SOS wafers are used in applications where the excellent electrical insulation properties of sapphire are required, such as shielding other circuits from stray currents induced by radiation. As these devices are usually fabricated on un-doped FZ-grown Si to utilise the high minority carrier lifetime properties, these wafers are usually made with un-doped EPI-grown Si offering similar properties.

At Inseto we use the parameters below to identify the SOS wafers. These are a hybrid of the SOI parameters and the silicon wafer parameters.

1. Diameter

As with the other wafer types this is the diameter of the SOS wafers in mm.

2. Material

This specifies the type of wafer, in the case of all SOS wafers this is SOS – Silicon on Sapphire.

3. Upper Material

The upper material of the SOS wafer, usually this is silicon.

4. Upper Thickness

The thickness of the upper material in microns (µm)   

5. Resistivity

The resistivity of the upper material. This is often critical for SOS-based devices as they are used as the basis of the fabrication for CMOS devices and circuits.

6. Dopant

This indicates if the upper material has been doped and what material has been doped into it. As with Silicon, the dopant is a material that has been deliberately implanted in the silicon to change the type of the silicon.

Typical N-type dopants are Phosphorus, Arsenic, and Antimony. These all provide an extra electron to the silicon which is then free to carry current.

Typical P-type dopants are Boron & Gallium. These have one less electron and so leave a ‘hole’ in the silicon lattice which is free to carry current.

7. Lower Material

The lower material of the SOS wafer, usually this is sapphire.

8. Cut of Lower Material

The cut of the lower material (sapphire wafer) from the original crystal, most common is R- plane as the position of Oxygen atoms in the Sapphire lattice is a good match for (100) Si and the resulting interface is free of defects such as stacking faults and dislocations.

9. Orientation of Plane

This is an additional metric for describing the plane of the lower material (sapphire wafer). For R-plane this is (1102).

10. Lower Material Thickness

The thickness of the lower material in microns (µm).

11. Polish

As with Silicon wafers this refers to the finish on the surface of the glass and can be either SSP or DSP.

12. –

13. Alignment, Coating Type, Coating Thickness and Other

The final 4 parameters we listed are alignment fiducial, coating type, coating thickness and other contain the same information as in the Silicon wafers.

Silicon on Sapphire Wafer Nomenclature

Sapphire Wafers

Semiconductor wafer selection: Sapphire wafers are a thin slice of single crystal sapphire that is widely used in the production of electronic and optical devices. They are characterised by a number of parameters, which affect their suitability and performance for a chosen task.

1. Wafer Diameter

Diameter of the wafer listed in mm. Typically wafers are talked about in inches; typical sizes are 2”,3”,4”,5”,6”,8”& 12” – with 2”,3” and 4” the most commonly used in industry and academia.

2. Growth Method

The growth method refers to the process by which the ingot of single crystal sapphire is produced. For most sapphire wafers this is the Kyropoulos method (abbreviated to Ky or Kr). The Kyropoulos method is a continuation of the Czochralski method (CZ) which is used in the manufacture of silicon wafers. The Kr method allows for the production of very large ingots of single crystal sapphire that can then be processed into wafers.

3. Crystal Orientation

Wafers are grown as single crystals that have an ordered, regular and repeating structure.  When they are sliced from the ingot the flat surface is aligned along one of several relative directions, known as the orientation. The orientation is classified by Miller indices as with silicon wafers but more commonly these are referred to by specific planes.

Typical cuts of sapphire are R-plane (1102), C-Plane (0001), A-plane (1120), M-plane (1010) and N-plane (1123). Orientation affects the physical properties of the sapphire wafers – and in particular how it integrates and lattice matches with other materials.

4. Thickness

The thickness of the sapphire wafer affects the mechanical properties and is typically expressed in µm (microns) and with a tolerance (± 20 µm). The tolerance is measured through a total thickness variation (TTV).

5. Polish

Wafer polishing is the final step in the manufacture of silicon wafers, which allows the production of a smooth, super-flat mirrored surface. There are two options for polishing: single side polish (SSP) and double side polish (DSP).

SSP: Only one face is polished, the second (the backside) is etched.
DSP: Both faces are polished, giving a high flatness to the wafer.

6. Alignment Fiducial

Alignment fiducial refers to the flats or notches used to identify the wafer. Originally flats were used to identify TYPE and well as ORIENTATION, but now there is less convention about what the flats mean and notches are quite common on 8” (200mm) wafers.

7. Other

At Inseto, we use Other to indicate if the wafers are laser marked with a unique identifier or if they have been stacked in a particular manner.

150mm Sapphire Wafers

Please visit our wafer store to “order semiconductor wafers online“.

Author

Date

Version

Author

Chris Valentine

Date

24 October 2019

Version

IKB046 Rev. 2

Download

The Heat’s Off

13th December 2019

DELO MONOPOX TC2270, a new specialist adhesive ideal for chip bonding – and other applications where electrically insulated heat transfer is required – is now available from Inseto.

Andover, United Kingdom – Inseto, a leading technical distributor of equipment and materials, is now supplying DELO’s new MONOPOX TC2270, a thermally conductive, electrically insulating adhesive, which is ideal for bonding silicon die and other applications where rapid heat transfer is essential.

For example, heat build-up is a common reason for integrated circuit failure and the efficient dissipation of heat in power semiconductors, as used increasingly in automotive applications, is a considerable challenge. With a specific thermal conductivity of 1.7 W/mK, DELO MONOPOX TC2270 ensures efficient heat transfer between die and packaging. It is also cheaper than silver epoxy, which has the often-unwanted property of being electrically as well as thermally conductive.

Supplied in 10ml syringes, DELO MONOPOX TC2270 boasts many other benefits too. For instance, the minimum curing temperature is 60oC in about 90 minutes, which means it can be used with temperature sensitive materials with little risk of introducing stress or causing warpage. In addition, it is a one-part adhesive, so no mixing is required and storage is at -18oC, a temperature accommodated by standard commercially available freezers; whereas most die-attach adhesives need to be stored in industrial freezers at much lower temperatures, such as -40oC.

Once cured, DELO MONOPOX TC2270 delivers a die shear strength of 60N/mm2 and has an end-application use range of -40 to +150oC, which is more than adequate for most silicon-based semiconductors.

Eamonn Redmond, Sales Manager of Inseto, comments: “The adhesive’s chemistry includes aluminium nitride, which ensures heat is quickly transferred away from the die, thus increasing the potential lifetime of the chip. Also, the fact that it is readily available in 10ml syringes means that users reduce the risk of having to dispose of out-of-date adhesive.”

In addition to its good shear strength, DELO MONOPOX TC2270 boasts a relatively high flexibility (11% compared to the less than 2% exhibited by most epoxies), making it ideal for bonding larger die. It also has a very low water absorption figure of just 0.1% and, once cured, volume resistivity is greater than 1xE14 Ohm cm and its surface resistance is greater than 1xE13 Ohms.

DELO MONOPOX TC2270 has an anticipated shelf life of six months. The datasheet for this adhesive, along with others from the DELO MONOPOX one-part, heat-cured epoxies range, can be viewed online at Inseto’s website, which also contains the datasheets of other adhesive types (chemistries, curing methods etc.) and an extensive Knowledge Base library of articles and guidance notes.

Redmond concludes: “The TC2270 is an extremely useful adhesive in the world of microelectronics and in any application where heat must be transferred without establishing an electrical connection.” Inseto is DELO Industrial Adhesives’ exclusive distributor in the UK and Ireland. Other products available through Inseto include an extensive range of UV cured or light activated epoxies, light cured acrylates, light / heat cured epoxies, dual curing materials, light / anaerobic curing adhesives, 2-part polyurethanes, 1- & 2-part epoxies, cyanoacrylates and single part silicones.

For further information on these products please visit: https://www.inseto.co.uk/adhesives.php.