Month: August 2021

Oxide Coated Wafer Overview – SiO2

11th August 2021

This article explains the types and primary properties of the most popular semiconductor oxide wafer coating, Silicon Dioxide (SiO2), and provides example applications.

Silicon Dioxide (SiO2) coatings provide a dielectric or passivation layer when applied to Silicon (Si), glass and other wafer types used in semiconductors, MEMS, BioMEMS, energy storage devices and other applications.

Correctly specifying the wafer type, its properties and the oxide coating applied, are key to the device being fabricated, functioning as intended.

Semiconductor wafers are primarily manufactured from one of the following materials:

All the above material types can be supplied with coatings of silicon dioxide (SiO2) or silicon oxynitride (SiOxNy) insulators. They can be coated with oxides on one or both sides and coat as well on the polished side, as they do on the etched finish side of a single side polished wafer.

The backside coating can be useful as a masking layer if you are planning to etch through to a layer or to devices fabricated on the front-side; and very good selectivity can be achieved with both wet and dry etch processes.

Wafers of any diameter from 50 to 300mm can be oxide coated with either SiO2 or SiOxNy and can be processed in small or large batch runs, or in single wafer scale reactors, depending on deposition growth rate and quantity of wafers required.

The process and some applications for each insulator material are listed below.

Atmospheric Thermal Oxide – ATOx:

This coating is one of the oldest semiconductor processes and dates back to the 1950s when Si was first required to be oxidised to produce the insulating layer in MOS devices.

The wafers are typically loaded in lots of 25 into quartz boats, which hold the wafers vertically with a defined space between them. The boats are then processed using tube furnaces where they are slowly heated (to prevent thermal stressing of the Si) to around 1020oC, which is the most commonly used oxidation temperature.

It is then held at this temperature for the time needed to grow the desired thickness of oxide, after which it slowly cools to the idle or room temperature and the boats are unloaded. This method of supporting the wafers during growth dictates that they are almost always oxidised on both sides, and the oxide has to be removed by protecting the front side with resist and striping the backside oxide off using buffered HF (BHF), until the surface becomes hydrophobic again when rinsed.

Si has a great affinity for O2 and the oxygen readily adsorbs onto the Si surface and is transported across the oxide to the Si interface, where additional SiO2 grows. Raising or lowering the growth temperature will raise or lower the growth rate significantly. The growth of this family of oxides was modelled by two scientists at Fairchild Semiconductor in 1965, B.E. Deal and A.S. Grove, and is known as the ‘Deal-Grove model’, used today to predict growth rate.

The oxide grown in this way is Stoichiometric and the refractive index is reliable (1.46 at 632nm). The colours of the films are also very reliable and can easily be viewed under white light and compared against a standard, widely available colour chart.

200 mm Horizontal oxidation furnace, courtesy of ATV GmbH
200mm Horizontal oxidation furnace (image courtesy of ATV GmbH)

There are two commonly used thermal oxidation processes; dry oxide and wet oxide.

Dry oxide is used when the desired oxide thickness is small, as the process is slow and the growth rate for <100> Si is typically 80 to at 1020oC. Raising or lowering the growth temperature will raise or lower the growth rate significantly. As the name suggests, a dry oxide process uses a dry source of molecular oxygen, such as a compressed gas tank. The oxygen tanks will have no water contamination and the resulting oxidation process produces a less porous SiO2 film.

A wet oxide process runs with steam as the precursor, which is obtained by bubbling the O2 feed-gas through a heated flask of DI water until it is saturated. The addition of H2O into the process increases the rate of growth for <100> Si to at 1020oC.

Hydrochloric acid (HCl) can be used for the removal of native oxide from the Si before oxide growth and this reduces the density of states at the oxide/Si interface and improves its performance as a dielectric. The presence of HCl also increases the growth rate of the oxide layer.

The presence of H in the wet process increases the transport rate across the oxide to the interface. The resulting oxide is grown both into the Si as well as on top of it at a ratio of 46% into the surface and 54% on top of the original Si surface. In other words, the overall wafer thickness does not increase by the depth of the oxide layer, as some of the Si is consumed during the oxidation process.

Another factor that influences the growth rate is the Si crystal orientation, with <111> Si having a growth rate of about 1.7x that of <100> Si. This is due to there being more Si atoms available on the <111> plane and hence the reaction with O2 is faster. Finally, highly doped Si (at about 10E19 to also oxidises faster than less doped Si.

Thermally grown oxide usually has compressive stress at the surface due to the differences in thermal expansion between Si and SiO2 and about 300MPa is typical.

Plasma Enhanced Chemical Vapour Deposition, PECVD SiO2:

This is the other most common oxide wafer growth technique and was developed as a means of growing good quality oxide coated interlayer dielectric material at relatively low temperatures, compatible with metallization schemes.

Precursors of Silane (SiH4) and N2O are mixed and then fed into a vacuum chamber and excited using a 13.56MHz RF source. The electrode with the wafers sat on it is held at 350 to 400oC and the oxide forms by a thermally catalysed reaction of the excited gas states to form SiO2. A liquid precursor, Tetraethyl Orthosilicate Si(C2H5O)4 (TEOS), can also be used. This avoids using Silane/Dichlorosilane and can also reduce the levels of stress in the SiO2 film.

Stress can be controlled by adjusting the SiH4:O2 ratio of the feed gases and ranges from 50 to 300MPa compressive, which is comparable to stresses produced by the thermal oxidation processes.

The growth rate is less dependent on orientation and doping level and the film composition can be adjusted to be tensile or compressive. Growth rates are typically in the 300 to 400nm.min-1 range, so it is a faster process than the higher temperature thermal techniques.

The key advantage of this technique is the lower temperature of growth which, at 350 to 400oC, is compatible with aluminium when used for interlayer dielectric and passivation. The main disadvantage (or advantage, depending on the number of wafers required) is that most of these reactors are cylindrical chambers with flat electrodes, so the number of wafers that can be processed simultaneously is much lower than in a tube furnace.


There are numerous applications of thermal oxide ranging from its use as an insulator, an implant or etch mask and an etch stop layer in SOI wafers, as well as part of a passivation layer stack. However, ATOx has some limitations due to the high temperature of growth so, in a passivation layer, the underlying metal layers must be refractory metals to withstand the growth temperature.

The optical properties make thermal oxide very good for photonics devices and also as a coating on Si wafers, which enable very good contrast to flakes of 2D materials that are exfoliated onto them, as well as providing underlying insulation for mobility measurements. An example of this can be seen below, where monolayers and a few layer graphene flakes just a few µm wide can clearly be seen.

A typical example of PECVD grown oxide is in very high integrity passivation layers, where the ability to add in NH3 to the process enables SiOxNy silicon oxynitride to be produced in a single process step, which produces an excellent passivation layer rather than growing sandwiches of SiO2 and Si3N4.

Single and Bi layer Graphene flakes on 90 nm of thermally grown SiO2, courtesy of Graphene Industries Ltd
Single and bi-layer graphene flakes on 90nm of thermally grown SiO2 (image courtesy of Graphene Industries Ltd)

In need of oxide coated wafers?

Inseto stocks, supplies and produces a wide range of coated wafer types and with different oxide thicknesses, on a fast delivery service. In addition, we can produce wafers with custom thickness oxide layers. The figure below shows our nomenclature chart for coated wafers:

Inseto’s nomenclature chart for Oxide and other Coated Wafers
Inseto’s nomenclature chart for Coated Wafers

Inseto’s oxide-coated wafers inventory can be found in our online store and further information about semiconductor wafers can be found in our Knowledge Base on our website. Further reading on oxide processes etc., can be found in: VLSI Technology, edited by S.M. Sze, the chapter on oxidation and online resouces including: Wikipedia and Libretexts.





Ian Burnett & Chris Valentine


11 August 2021


IKB082 Rev. 1


Sintered Die Attach for High Power Devices

3rd August 2021

An overview of Sintered die attach of power electronic SiC semiconductor’s, where sinter materials replace solder in high temperature applications. (IKB-084).

Why use sintered die attach?:

Electric and hybrid electric vehicles (EVs and HEVs) are creating a huge demand for power modules. They are also demanding lots from the modules, such as the ability to switch high voltages at high frequencies into loads that draw hundreds of Amps.

Deep power cycling is expected too. For example, thousands of maximum accelerations must be accommodated by channelling power from the battery pack to electric motors, as well as channelling energy back to the pack during regenerative braking.

Also (and as is the norm for the automotive sector), compact and lightweight form factors are required. So too is high reliability operation in harsh environments; in which temperature extremes and mechanical shocks and vibrations will be experienced.

Indeed, if you compare the requirements for consumer, industrial and automotive applications there are significant differences. Consumer electronics are designed to operate in a mild environment (0 to 40oC temperature range and low humidity), a typical product life expectancy of two to five years is normal and failure rates of up 10% are considered acceptable. Industrial electronics must operate in a relatively harsh environment (-10 to 70oC temperature range and higher humidity levels), a typical product life expectancy of five to 10 years is required, and failure rates should be well below 1%.

Automotive electronics is almost pushing into the realms of the military world. Systems, modules and components must (certainly for the powertrain), operate in an extremely harsh environment (-40 to 160oC and 0 to 100% humidity), a life expectancy of up to 15 years is demanded and the goal is to have 0% failures. Also worthy of note is that many vehicle OEMs are now stipulating ‘zero reworks’, putting great pressure on the manufacturing and test processes of their suppliers.

High power

From a power perspective, silicon carbide (SiC) is today’s semiconductor material of choice for use in power modules, which typically contain several metal oxide semiconductor field effect transistors (MOSFETs) or insulated gate bipolar transistors (IGBTs) as the main power switching devices. For example, Tesla is recognised as one of the first mainstream vehicle manufacturers to embrace SiC-based power modules. Its Model 3 has a power inverter that includes 24 SiC-based power modules from STMicroelectronics. Each module has two SiC MOSFETs.

The increased use of SiC is part of the power semiconductor industry’s roadmap. For example, according to one integrated device manufacturer (IDM), in the early 1990s, a silicon (Si) IGBT fabricated on its 220µm process would have had a power density of circa 30kW/cm2. As the IDM’s fabrication geometries shrank, device power density increased to about 70kW/cm2 by the early 2000s. Most recently, switching from Si to SiC and to a 90µm process has enabled the IDM to achieve a power density of 250kW/cm2.

Clearly, smaller and thinner dies mean a reduction in chip size and cost, higher efficiency (through lower losses) and an increase in power density. However, despite power losses being lower for SiC than for Si, these are relative to that higher power density.

Far more heat needs to be dissipated than before, and that is a challenge for device packaging.

The maximum operating temperature of a standard, plastic-encapsulated component (say in a TO 247-4 form factor) tends to be governed by its package. While some have a maximum operating temperature of 175oC, this is far below the temperature at which MOSFETs and other switching structures fabricated using SiC have been proven to work. The maximum operating temperature is limited by properties of the plastic package and the adhesives or solders therein.

To benefit most from SiC’s ability to operate at a high temperature, it is best to attach bare die to a substrate that will provide good heat dissipation. Indeed, another advantage of SiC over Si is its high thermal conductivity, between 3 and 4W/(cm2.K) compared to 1.5 4W/(cm2.K).

The die must be metallised on the backside before it can be placed. This tends to be a tri-metal metallisation – adding a layer of titanium, then nickel, then silver (or sometimes gold). Bond wires, from the top of the die to module pins, have a role to play in heat dissipation. For standard high power electronic devices, aluminium wire or ribbon is used. The thermal conductivity of aluminium is about 2.3W/(cm2.K). For SiC, copper (or copper clad in aluminium) is used. Its thermal conductivity is about 4W/(cm2.K) and its electrical conductivity is better too.

A popular substrate is copper and for most applications, die can be soldered in place. Once again though, SiC pushes the envelope. The thermal conductivity of solder is not that good (circa 25W/(m.K) for lead-free solders, such as SnAg and SnAgCu) and its melting point is circa 220oC.

The pressure’s on

An alternative to soldering is sintering (sintered die attach). A paste comprising monometallic particles (of less than 1um in size) and a resin is printed, in the same way solder paste is applied to a PCB, onto a substrate in patterns corresponding to the shapes and locations of the SiC dies.

The substrate is heated to evaporate the resin and the dies are placed. The sintering process – which is often performed in an inert atmosphere (or on rare occasions a vacuum) to prevent the oxidisation of metal surfaces – is a combination of heat and pressure (a downwards force onto the tops of the dies).

The pressure, which can be up to a few tens of MPa, serves two purposes. Firstly, it means a lower temperature can be used to bond the materials, yet the bonds achieved will be able to operate at a higher temperature in the field. Secondly, it reduces the risks of voids, the presence of which are measured as a percentage of die area. Even a small void percentage can lead to delaminating and cracking over time, and a delaminated die can result in catastrophic failure because of the high currents being switched.

Silver is currently the most popular sintering material. Its melting point is about 960oC and the thermal conductivity of a sinter paste is between 130 and 250W/(m.K).

Most sintering tools use a single, flat punch to apply force to the tops of the dies. However, die thickness will vary so the sinter material will not be compressed to the same extent for all dies. Multi-punch systems use multiple punches to apply force to groups of dies, but the problem still remains of accounting for different die thicknesses within each group. The solution, according to AMX Automatrix, is to have a single punch for each die; a solution the company has implemented in its patented micro-punch sinter tool (see figure 2).

While most sintering uses direct bonded copper (DBC) or ceramic substrates, research is being done into alternative substrates. According to a paper presented at the 11th International Conference on Integrated Power Electronics Systems (Berlin, Germany – March 2020) these alternatives include insulated metal substrates (IMS), copper lead-frames and high temperature stable PCBs.

As mentioned, and irrespective of the substrate onto which the dies are sintered, the contact between surfaces must be as near perfect as possible. There should be no voids. However, checking for voids requires the use of a scanning acoustic microscope (SAM) because x-ray equipment does not work – or rather the power required to penetrate the metallic substrate is so high it makes the die virtually invisible.


Sintered die attach is undoubtedly the manufacturing process of choice for power modules that employ (and want to get the most from) SiC dies. The sinter must be as free of voids as possible if the module is to provide the performance and long-term reliability demanded by the EV and other sectors. Minimising the risk of voids beneath multiple small dies when sintered in a single process step requires multi-punch tools, and verification requires the use of SAM technology.

This “Knowledge Base” document was first published in e-mobility technology magazine’s “Issue #9 Summer Edition” and is reproduced here with kind permission of the editor.

Sintered Die Bonding of Semiconductor Devices
Example: Sintered Die Bonding of Semiconductor Devices

Sintered Die Attached Flat Tooling
Example: Traditional Sintering “Flat” Tooling

Sintered Die Attach Micro-Punch (AMX Patented) Tooling
Example: Advanced Sintering “Micro-Punch” Tooling (AMX Patented)

Manual Sintered Die Attach System
AMX P51 Manual Sintered Die Attach System

Semiautomatic Sintered Die Attach System
AMX P100 Semiautomatic Sintered Die Attach System

For further information on our range of sinter die bonding equipment, please click HERE.





Jim Rhodes


03 August 2021


IKB084 Rev. 1


Sintering SiC Die Attach for High Power Electronic Devices

3rd August 2021

Example: Sintering SiC Die Attach of Semiconductor Devices

Check out the our latest “Knowledge Base” article on sintering SiC die first produced for e-mobility technology magazine (Summer Issue #9) and reproduced with kind permission of the editor on our website.

Silicon carbide (SiC) is the semiconductor material of choice for high power semiconductor transistors. They can switch far higher voltages and currents than devices fabricated from silicon. They can also run much hotter, presenting packaging challenges.

A popular substrate on to which SiC die is attached is copper. It is a good conductor of power and heat. However, the thermal conductivity of a typical die attach solder is not great, and melting points max out at circa 220°C.

An alternative to soldering is sintering. A paste comprising monometallic particles and a resin is printed onto a substrate in patterns corresponding to the shapes and locations of the SiC dies. The substrate is heated to evaporate the resin and the dies are placed. The sintering process itself sees a combination of heat and pressure.

Inseto is exclusive distributor for AMX’s range of equipment for sintering of die and leadframe assemblies, plus automatic inline acoustic microscopy. in the UK, Ireland and Nordic regions.