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Knowledge Base Fact Sheet

What Is A Wafer Bonder?

4th March 2021

This document overviews the wafer bonder and its use in semiconductor device fabrication (IKB-080).

What is a wafer bonder?

A wafer bonder is a precision machine tool used in the fabrication of micro-electrical mechanical systems (MEMS) and other similar technologies. A wafer bonder is used to package together two or more substrates on the wafer-level.

Wafer bonders are used on both R&D and industrial scales when the mechanically stable joining, or bonding, together of two substrates is required. This bonding process can either be temporary or permanent, and a number of methods and technologies have been developed depending on the substrates involved and the applications required. For more information on the commonly used bonding methods, see Inseto’s knowledge base document Wafer bonding methods.

A wafer bonder works by controllably bringing together the desired substrates and applying some combination of force/pressure, heat or current as required by the bonding method. In some cases, a wafer bonder is required to keep high levels of alignment between the two substrates that are being bonded. As such, the wafer bonder is a complex system requiring high levels of precision and control.

The wafer bonder is required to control the surrounding conditions of the bonding environment to ensure the highest quality of bond can be achieved. The critical environmental factors to control are:

  • Bond Temperature
  • Ambient Pressure
  • Applied Force

To ensure the tightest control over all of these factors, the leading wafer bonders utilise a dedicated bond chamber within which the bonding process takes place.

Bond Chamber
The bond chamber is a sealed region within the wafer bonder that can be evacuated to the user specified pressure and heated or cooled to the required bond temperature. A high quality bonder will exhibit high temperature uniformity and repeatability and precise control over the pressure within the chamber.

The sealed bond chamber, sometimes referred to as the process chamber, should be contamination free to further enhance the quality of the bond interface. The design of the bond chamber is specific to the manufacturer but all good wafer bonders are designed such that the chamber is minimally exposed to the surrounding external environment. This is controlled by the wafer or substrate loading mechanism.

Loading Mechanism
The loading mechanism is responsible for the transfer of the substrates into the bond chamber. As such, the design of this transport fixture is crucial to maintaining the cleanliness of the chamber and thus the quality of the final bond. A loading mechanism, which reduces the opening of the chamber and minimises the number of parts inserted in the chamber, will keep the introduction of contaminants to a minimum.

A further requirement of the loading mechanism is that if the wafers are aligned relative to one another, the precision of this alignment is not lost in the transport into the chamber or in the bonding process. This brings us to the third component required for a quality wafer bonding solution, the alignment of the wafers.

Alignment
The alignment of the two wafers to one another and how this alignment is maintained is crucial to many sectors where wafer bonding is required such as MEMs. There are several methods employed to align the wafers, in some systems the alignment is carried out in-situ (within the wafer bonder), in others, the alignment is carried out in a complementary tool, such as a mask aligner or bond aligner. If processed in a mask aligner, the now aligned wafers, commonly referred to as a stack, must be transferred to the wafer bonder by some form of fixture or carrier that preserves this alignment.

Both approaches, either within the wafer bonder or in an external aligner, have their advantages and disadvantages. However aligning outside the wafer bonder can allow facilities to make use of previous capital investment whilst also reducing the complexity required of the wafer bonder. Furthermore, this separation of alignment and bonding can also lead to an increased efficiency of operator time. As the alignment step is usually a much shorter process than the bond but requires more input from the operator, a number of wafer stacks could be aligned at one time and then all transferred to the bonder. The wafer bonder will then process without any further input from the operator freeing them to complete other tasks.

Bond Plates
The final component to be discussed when considering what constitutes a high quality wafer bonder are the plates that transfer the force to the wafers as they are bonded. In some systems these plates can be referred to as wafer chucks. The plates are located within the bond chamber and are crucial to ensuring a uniform bond across the whole wafer.

As shown in the diagram below, the bond plates both transfer the force to the wafers but are commonly used to heat the bonded stack, if heat is required for the bond method used. A highly repeatable application of force to initiate the bond across the whole area to be bonded is necessary for all applications. The plates must have high levels of planarity and flatness and depending on the design of the bonder, the force can be applied either through the top, bottom or via both sets of plates.

For further information on our range of Wafer Bonders, please click HERE

Author

Date

Version

Author

Chris Valentine

Date

04 March 2021

Version

IKB080 Rev. 1

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Knowledge Base Fact Sheet

Resist Coating Methods

10th November 2020

This document provides an overview of techniques for the uniform coating of a substrate with photoresist (IKB-067).

Resist Coating Methods:

A crucial requirement to ensure repeatable, reliable and acceptable results with photolithography, is to have a uniform coating of a photoresist over the surface of the substrate. Photoresist is typically dispersed in a solvent or aqueous solution and is a high viscosity material. There are a number of options available to coat a photoresist depending on the process requirements:

  • Spin-coating
  • Spray-coating
  • Dip-coating
  • Inkjet printing
  • Slot-die coating

Spin- coating:

Spin-coating is the most common method used when coating a substrate with photoresist. It is a method that presents a high potential for throughput and homogeneity. The principle of spin-coating is that typically a few millilitres of photoresist are dispensed on a substrate which is spinning at several 1000 rpm (typically 4000 rpm). The resist can either be dispensed when the substrate is stationary and then accelerated up to speed (static spin-coating), or it can be dispensed once the wafer is already rotating (dynamic spin-coating). Any excess resist is spun off the edge of the substrate during the spinning process.

The centrifugal force experienced by the resist on the surface of the wafer causes the viscous resist to spread out into a uniform thin film. The height of this film is directly controlled by the rotational speed of the substrate, allowing the operator to achieve the desired film thickness.

Alongside the spin speed the spin time can also be used to control the film thickness. This is due to the evaporation of some of the solvent or aqueous liquid used to disperse the resist, which causes further thinning of the resist. The loss of the solvent also results in the stabilisation of the film, so that it will not collapse during later handling of the substrate.

The main advantages of spin-coating are that the coating step is quite short, typically 10-20 seconds, which when combined with the dispensing and handling time, can lead to process times less than 1 minute. The other advantage is that the films obtained are very smooth and the thickness can be reproducibly controlled very accurately.

The disadvantages and limitations of spin-coating arise when using non-circular substrates or thick (very viscous) resists. In these cases the air turbulences at the edges and especially the corners cause the resist to dry in an accelerated manner. This excess drying then supresses the spin-off of the resist from these regions, causing a bead of resist to build up at the perimeter of the substrate; this built up sidewall of resist is referred to as an edge bead.  In more advanced spin-coat systems, techniques for removing this edge bead by precise application of solvent, or limiting its growth by controlling the air turbulences, have been developed.

The other limitation that can impact spin-coating is if the surface of the substrate has a large number of features or a varied topography, then the homogeneity of the film thickness can be affected. With build-up of resist in holes or spaces leading to thicker films and thinner films on the edges of the features. This can be overcome by a two-stage spin profile, or by using one of the alternate coating techniques.

Spin Coat Nozzles for Automatic Dispensing of Photo Resist
Spin Coat Nozzles for Automatic Dispensing of Photo Resist

Spray-coating:

Spray-coating is an alternative to spin-coating, particularly when the substrate surface or morphology means that the photoresist cannot be coated with the required uniformity. The basic principle of spray-coating is that the resist film is formed from the deposition of photoresist that is atomised into droplets in the µm range.

The formation of the droplets is possible through a variety of techniques; the simplest is to produce an atomised spray from a nozzle similar to what is used in a conventional airbrush gun and a nitrogen nozzle. Nitrogen is preferred, as it helps to reduce contamination of the resist with humidity or particles and produces a dryer mist of droplets.

The second standard method to generate an atomised spray is through the use of an ultrasonic atomiser. The ultrasonic atomiser creates the droplets of resist via the high frequency mechanical vibration of the resist media, which is then transported to the substrate by a carrier gas.

The droplets of resist are then deposited on the surface of the substrate where they form a continuous thin film of the photoresist. Spray-coating is thus able to cover the entire surface of the substrate even in arbitrary shapes and to provide a conformal coating regardless of the topology. Additionally, there is less photoresist wasted allowing for a higher yield in comparison to spin-coating.

To be able to spray-coat a photoresist, the resist must have a suitably low viscosity. Typically this is a few cSt and may require the dilution of the resist with a solvent. Dilution of the resist can lead to the resist ageing process accelerating and to particle formation within the media.  The other limitation of spray-coating, is that formation of films <1 µm is difficult given the stochastic distribution of droplets landing on the surface. To form a continuous film requires a minimum critical resist droplet density to be reached, which increases the minimum film thickness as well as increasing the processing time.

Schematic of a typical Spray Coat process.
Schematic of a typical Spray Coat process.

Dip-coating:

Dip-coating is used as a solution for resist coating if the size and type of substrate is not suitable for spin-coating and the photoresist represents a significant cost to the overall process, that even when compared with spray-coating, the consumption of resist must be further reduced.

The process of dip coating is that a wafer is submerged vertically in a cuvette of resist and lifted out slowly. The resist film then forms on the surface and thins out as the substrate is removed from the bath of photoresist. The thickness of the resist is controlled by the dwell time in an atmosphere saturated with solvent, which controls the rate of solvent evaporation. The higher the withdrawal speed from the resist bath, the thicker the photoresist film.

As a result of this process, the yield of resist can be 100% if both sides of the substrate need coating, representing a huge increase in resist yield compared to spin and spray-coating. The tank may have to be replaced if the resist expires before it is consumed, which will decrease the yield but still offers the most cost effective of the three coating methods covered.

The photoresist often must be significantly diluted, which can significantly increase both the ageing of the resist film and the frequency with which the tank must be replaced. Additionally, substrates with large changes in surface topography are not suitable as the resist can flow over the substrate and significantly reduce the surface homogeneity.

Schematic of a Dip Coating process.
Schematic of a Dip Coating process.

Inkjet printing:

An alternative method utilised to dispense resist is ink-jet printing. This works in a similar fashion to spray-coating, producing droplets of photoresist. Unlike spray-coating however, these drops are produced in a stream rather than a mist. This stream of droplets can then be precisely controlled and patterned onto the substrate.

Ink-jet printing differs from the other coating methods, in that whilst it can be used to produce a thin homogeneous film of photoresist, the real advantages in its use come from using it to directly pattern the substrate. This can dramatically save the amount of resist used by only depositing where required, reducing both the cost and environmental impact of the photolithographic process. Additionally, it is possible to directly deposit some materials such as organic semiconductors and conductive inks onto the surface, without needing to run a photolithographic process.

The disadvantages of the increased flexibility and versatility of ink-jet printing, are an increased coating time leading to a reduced throughput of coated wafers and substrates. This can be offset however through the use of multiple print-heads and path optimisation. Additionally, ink-jet printing is not the ideal solution for the coating of thicker resists, as the layer thickness is typically only a few microns.

Schematic of a Inkjet Coating process.
Schematic of a Inkjet Coating process.

Slot-die coating:

The final method of coating photoresist discussed here is slot-die coating. Slot-die coating is a scalable manufacturing technique used in a range of industrial processes to produce uniform films and coatings. The principle of slot-die coating is shown in the image above. The print-head continuously dispenses the photoresist onto the moving surface of the substrate, producing a uniform film of photoresist. As the solvent within the wet photoresist evaporates, the photoresist film dries leaving a uniform thin film that can then be processed further.

Slot-die coating is a pre-metered coating technique; this means that all the material that is dispensed from the print-head of the coater is used to coat the surface of the substrates. This enables very low (to no) levels of photoresist wastage, which is a great advantage if the photoresist represents a large material cost.  The other advantages of slot-die coating are that it is a readily scalable technique, allowing the number of substrates to be greatly increased. Slot-die coating is also perfectly suited to coating flexible substrates and to being used in a roll-to-roll manufacturing process. Beyond the coating of photoresists, slot-die coating (like ink-jet printing) can be utilised to coat any functional material that can be dispersed into a printable ink.

Schematic of a Slot-die Coating process.
Schematic of a Slot-die Coating process.

For further information on our range of Spin Coaters, Spray Coaters & Inkjet Printers please click HERE

For further information on our range of Slot-die Coating Equipment please click HERE

Author

Date

Version

Author

Chris Valentine

Date

10 November 2020

Version

IKB067 Rev. 1

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Knowledge Base Fact Sheet

What Is Spin Coating?

4th November 2020

This document overviews the semiconductor fabrication process known as “spin-coating” and explains how it works (IKB-075).

What is spin coating?

Spin-coating is the most widely deployed method for dispensing photoresists and other materials uniformly onto substrates. Spin-coating is used to produce thin films of the desired material with high levels of process control and repeatability.

Photoresist as discussed in the lithography basics knowledge base document is crucial to the photolithography process. Typically, photoresist is a highly viscous material and the uniformity of its coating plays an important role in the reliability of any photolithography process, as well as the resolution achievable. Spin-coating is a technique widely used in research, development and industrial processes, in order to produce specific uniform film coatings.

The principle of spin-coating is that a few millilitres of photoresist are dispended onto the substrate. The substrate is then spun at high speeds in the range of 500 – 4000 rpm. The viscosity of the photoresist is then selected to keep the spin speed in the optimal range whilst producing a coating of the required film thickness. These parameters are usually specified by the resist manufacturer and are specific to the resist used. The other source of information for these parameters is to research the wide body of literature about photolithography and to adapt a published process to your needs.

The photoresist is dispensed at the centre of the substrate prior to the spinning, this is called static dispense. An alternative to this is dynamic dispense, where the wafer is already spinning at the desired speed and to then dispense the photoresist. This is the more commonly used technique when spin speeds are in excess of 1000 rpm.

At these high spin speeds the centrifugal force causes the viscous solution to spread outwards and flow towards the edge of the wafer. At the edge material builds up until the surface tension of the photoresist solution is overcome, at which point the resist is ejected from the spinning wafer. The thickness of this thin film is defined by a number of parameters: spin speed, concentration, viscosity and spin time.

The requirements for uniformity are demanding on the spinning process, as the quality of the film is critical to the number and size of defects in the pattern transferred. Photolithographic processes can require high uniformity, both across a single wafer and from one wafer in a cassette to another. With typical photoresist film thicknesses of 2 µm, this is a uniformity requirement of ±1.0%.

To achieve results with uniformity to this high tolerance the spin speed and time must be precisely controlled, as well as the acceleration of the wafer up to the specified spin speed. In some cases a multi-speed spin protocol is recommended by the resist manufacturer, this is to ensure that the final resist thickness is finely controlled and within the tolerances required for further processing.

Pictorial Representation of Photo Resist Spin Coating





For further information on our range of Spin Coaters, please click HERE

Author

Date

Version

Author

Chris Valentine

Date

04 November 2020

Version

IKB075 Rev. 1

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Knowledge Base Fact Sheet

What Is A Mask Aligner?

1st July 2020

This document overviews the mask aligner and its use in semiconductor photo-lithography (IKB-068).

What is a mask aligner?

A mask aligner is a precision machine tool used in the semiconductor manufacturing process to transfer a pattern onto a wafer or substrate; these patterns are micro and nano in scale.

The patterns (structure) are created using a shadow transfer method, where the pattern (photomask) to be printed is placed between a light source and the substrate to be patterned (wafer). The substrate being patterned is first coated with a photosensitive material (photoresist), this material then reacts to the light projected from the shadow image. The resultant pattern is then developed using specific chemicals.

This process is commonly known as photolithography, more details of this micro-fabrication technique are covered in a separate document Photo Lithography Basics.

Mask aligners enable photolithography to be used to produce semiconductor devices, such transistors, sensors and medical components, etc.

Along with a method to uniformly coat the substrate with photoresist, a mask aligner is crucial to the photolithography process. A mask aligner is used to both precisely align the coated substrate to the photomask containing the structure to be patterned, and for then exposing the substrate with light to transfer the desired pattern onto the substrate.

In order to enable this complex process to take place and to produce structures with features down to 250nm, the mask aligner must be a precision engineered instrument. As these structures are so small, the wavelength of light used is also a factor in determining the final feature size.

The key components of a mask aligner include the following:

  • Ultraviolet light source
  • Optical elements
  • Mask holder
  • Substrate holder
  • Microscope

Ultraviolet light source:

A mask aligner would not be able to expose a substrate to light in a controllable manner, if it does not have a high-quality source of light. Traditionally, this has been a broadband mercury bulb, which provides a spectrum of light (see “Emission Spectrum of a typical mercury lamp” graphic). Despite two wavelengths being outside the specific UV spectrum (100-400nm), mask aligner light sources are commonly referred to as being UV, as the bulb also transmits in this range.

Dependent upon the photoresist used, the light should be transmitted in either the broadband range, or in a specific spectrum G: 436nm, H: 405nm or I: 365nm.

An alternate option to a mercury lamp is to use a UV LED array. These contain a number of LEDs that emit light at the G, H or I line wave-lengths, or a combination of all three to produce a similar broadband spectrum to that of the mercury bulb.

UV LEDs have seen advances in quality and performance in recent years, enabling them to replace the traditional mercury bulb. The introduction of the UV LED has brought a number of advantages. The first of these is a reduction in the power consumption of mask aligners, which brings with it a reduced running cost. In addition, the removal of mercury from the production facility brings health and safety benefits to the operator, plus there is a reduction of the volumes of mercury that must be safely disposed of when lamps reach the end of their lifetime. Other benefits include reduced maintenance, as the LED’s are only illuminated during the exposure period; thus no shutter mechanism is required, plus simplified facility requirements, since no additional cooling or extraction are needed with LED light-sources.

Optical elements:

After the UV source the light passes through a number of optical elements. These optical elements are used to shape the beam of light so that there is uniform illumination across the substrate to be processed.

Typical optical elements include:

  • Ellipsoidal Mirror
  • Cold Light Mirror
  • Heat Sink
  • Shutter
  • Fly’s Eye
  • Condenser Lens
  • Filter Plates
  • Front Mirror
  • Front Lens

The quality of these optical components is critical to the resolution achievable by the mask aligner. Without high quality lenses and mirrors that are kept in good condition and free of scratches or contamination, the resulting lithography will not be homogeneous over the whole substrate. There will be changes in the critical dimensions (CD), under or over exposed photoresist and overall a loss in the yield of functional devices.

Mask holder:

The mask holder is the component that holds in place the photomask containing the pattern to be transferred to the substrate. The mask holder must not allow the photomask to move whilst alignment and exposure are taking place.

Substrate holder:

The substrate holder, often referred to as the wafer chuck, holds the substrate in position within the mask aligner. The substrate is usually held in place by applying a slight vacuum to the chuck and with alignment pins used to mark the rough placement. The substrate holder can then be moved around relative to the mask holder, this allows the precise alignment of features on the mask to existing features on the substrate.

The substrate holder also compensates for any wedge or slope on the surface of the substrate through a process called Wedge Error Compensation (WEC). The WEC is crucial to ensure uniform results across the whole substrate. WEC is the process of ensuring the top surface of the wafer is parallel to the photomask and so the optical path travelled by the UV light is the same regardless of position on the wafer.

Microscope:

The microscope system within the mask aligner allows the user to view the photomask and the substrate and to align the relevant features to one another. Typically, there are two microscope arms which are used to locate the alignment targets on the substrate and the mask, and to then move the substrate on the wafer chuck into position.

Summary:

The quality of these five components outlined above will determine the resolution and alignment accuracy of the lithographic process.

Critical to the final resolution of the features being printed are a well-defined UV source and optics that reduce optical diffraction limitations and ensure uniformity of the light across the whole wafer.

The mask holder and substrate holder together are critical to the alignment accuracy, this is key when fabricating complex devices with many layers which must be aligned to one another.

If employed in a production environment, all elements of the mask aligner can be automated using pattern recognition to detect alignment targets and to correctly orientate the substrate and the mask, in addition to wafer and mask handling systems, to automate the loading and unloaded processes.

Mercury Lamp Emission Spectrum
Emission Spectrum of a typical mercury lamp





SUSS Mask Aligner with LED Light Source
SUSS Mask Aligner with LED Light Source









Example Semiconductor Wafer Lithography
Example Semiconductor Wafer Lithography

For further information on our range of Mask Aligners, please click HERE

Author

Date

Version

Author

Chris Valentine

Date

01 July 2020

Version

IKB068 Rev. 1

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Knowledge Base Fact Sheet

Imprint Photolithography

4th May 2020

An overview of Micro and Nano Imprint Photolithography (IKB-054).

Imprint photolithography is a key technology for many emerging applications such as micro-optics, augmented reality, MEMS and optoelectronic sensors; but what is it and how does it work?

Photolithography, be that optical, electron-beam or imprint, is the process of transferring a pattern from one object onto another. Electron-beam and optical photolithography are used to transfer a two-dimensional pattern either from a photomask or a computer program onto a substrate. Imprint photolithography is concerned with the transfer of three-dimensional patterns and structures to a substrate.

A typical imprint photolithography process consists of the following steps:

  • The wafer is coated with an imprint resist and aligned with a stamp
  • The wafer and stamp are brought into contact and the resist fills the cavities in the stamp.
  • The resist is solidified through UV cross linking or an external thermal source
  • The stamp is removed and the resist is left imprinted with the desired pattern.

Imprint Lithography Process
Imprint Photolithography Process

Crucial to the imprint process is the fidelity of the stamp containing the 3D pattern. Typically, this design will have submicron features that need to be reproduced to a high tolerance. The process for producing these master stamps can be lengthy and expensive, so precise control of the imprint and removal are required to ensure no damage to the stamp. Often, to protect the master copy of the pattern, the stamp used in day-to-day fabrication is an imprinted replica. This stamp will do many hundreds of imprints before it must be replaced, as the integrity of the surface slowly degrades and the yield of the devices produced decreases.

The limitations of imprint photolithography are three-fold. The first, as addressed above, is that the imprint will only be as good as the quality of the stamp. As such, much research and time is spent by leading manufacturers to improve the fidelity of stamp replication and the subsequent coating of the stamp with anti-sticking layers.

The second limitation is in the imprint and exposure process, again equipment manufacturers are constantly innovating and bringing the alignment accuracy to <1 µm for patterns that can be microscale or nanoscale. Leading manufacturers have now developed techniques that allow the same technology to be used to imprint microscale features i.e. features from the millimetre level down to the micron level and to imprint features less than 100 nm. Previously, this wide process range would have required multiple equipment installations.

The third and final source of limitation is in the resists used to imprint with. These must be able to flow into the cavities of the stamp, be curable either by heat or light and have fast curing times, so that high device throughput is possible as processes scale up to manufacture. The resist materials must also be able to reproduce the high aspect ratios required of them, whilst possessing precise other physical properties, such as refractive index or electrical conductivity. As with the tool requirements, the chemical manufacturers are constantly improving and producing new materials to push this field forwards and enable scalable imprint lithography to be a reality in a production environment.

Imprint photolithography is a mature technology suitable for fabricating three dimensional structures, where definition and precision are key and can be deployed whether the features are of mm, µm or nm scale.

For further information on our range of equipment for Imprint Photolithography, please click HERE.

Author

Date

Version

Author

Chris Valentine

Date

04 May 2020

Version

IKB054 Rev. 1

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Knowledge Base Fact Sheet

Photolithography Exposure Modes

4th May 2020

A guide to photolithography mask aligner exposure modes (IKB-053).

This Inseto Knowledge Base document introduces the Mask Aligner Lithography Exposure Modes. The basic steps of photolithography as used in microfabrication, are outlined in a separate document: Lithography Basics.

In this guide, some more detail will be given on the exposure of a coated wafer or substrate and how this affects your photolithography process.

A mask aligner is utilised in photo lithography to align the coated wafer with a mask and then to expose the wafer to UV light through the mask, as shown.

When exposing the coated substrate to the UV light, there are a number of options available to the user called lithography exposure modes.

Through the mask aligner, the operator is able to precisely control the height of the gap between the mask and the wafer, called the “exposure gap”. Increasing or decreasing this gap will impact on the final resolution of the patterned substrate but also the throughput of the fabrication process.

The exposure modes can be split into two groups: contact and proximity exposure.

Commonly used contact exposure modes are:

  • Soft contact
  • Hard contact
  • Vacuum contact
  • Low vacuum contact

In contact mode, the mask and the wafer are, as the name suggests, brought into contact and then held parallel to one another through a process called wedge error compensation (WEC). The wafer and mask are then moved to the alignment gap and positioned relative to one another. Once alignment of the mask and the wafer has been completed, they are then pressed together and exposed to the UV light. The extent to which they are pressed defines the exposure mode and the resolution achievable.

Exposure Mode: Soft contact
In soft contact the wafer and mask are only just brought into contact and no further force is applied.

Exposure Mode: Hard contact
In hard contact, the wafer and mask are brought into contact and then an external force or pressure is applied to press them into one another. The amount of force used should be defined by the operator.

Exposure Mode: Vacuum contact
In vacuum contact, the wafer and mask are pressed together as in hard contact, but then a vacuum is pulled between the wafer and the mask bringing them closer together. This results in the highest resolution results. Low vacuum mode (sometimes referred to as soft vacuum mode) reduces the impact on the wafer and mask when the vacuum is pulled. This is particularly useful if brittle substrates are being used that are liable to break.

Exposure Mode: Proximity
The alternate to contact exposure is to use proximity exposure. Here the mask and wafer never touch and are held apart from one another. The exposure gap setting can range from a few microns up to 100s of microns, depending on the quality of the mechanics and optics within the mask aligner in use. Within a proximity exposure even the WEC is carried out without the wafer and mask touching.

As we move from proximity; to soft; to hard; to vacuum contact the resolution achievable increases. This is because as the wafer and mask are brought into contact, the diffractive effects from mask to air and air to substrate (which lower resolution) are minimised / removed, until the exposed pattern more precisely matches that of the wafer.

However, repeated contact exposures increase the risk of contamination and damage to the mask. This could be from particles transferred from the substrate to the mask in the form of dust, or other organic and inorganic contaminants; partially baked photoresist residue from the substrate can also stick to the mask. In these circumstances, the fidelity of the pattern is compromised and the yield on the substrate is lowered. To overcome this contamination, the mask must be cleaned after a set number of exposures.

Advances in the optics within the mask aligner have led to improvements in the resolution achievable at large gaps, making proximity exposure the most common exposure mode used in a production environment today.

Lithography exposure of wafer and mask within a mask aligner
Lithography exposure of wafer and mask within a mask aligner

For further information on our range of equipment for UV Lithography, please click HERE.

Author

Date

Version

Author

Chris Valentine

Date

04 May 2020

Version

IKB053 Rev. 1

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Knowledge Base Fact Sheet

Semiconductor Wafer Nomenclature

3rd May 2020

This article explains the nomenclature used to identify our semiconductor wafer types and specifications, along with the key descriptive criteria to consider when choosing wafers (IKB-044).

Semiconductor wafer selection is key to a successful use of wafers and substrates for your process. Wafers are manufactured with very high precision, with attributes specific to the electronic and mechanical properties and any coatings applied after manufacture.

Wafers are manufactured from four main materials:

  • Silicon
  • Glass and Fused Quartz
  • 3-5 or 2-6 Compound Semiconductors
  • Sapphire

The figure below describes Inseto’s nomenclature chart for Silicon wafers:

Silicon Wafer Nomenclature
Silicon Wafer Nomenclature Chart

The second category of wafers we classify is coated wafers. These are wafers with an added layer either on both the top and bottom surfaces of the silicon or just one of the surfaces – usually the top.

The figure below shows Inseto’s nomenclature chart for Coated Wafers:

Oxide and Nitride Coated Wafer Nomenclature
Oxide and Nitride Coated Wafer Nomenclature Chart

The third category of wafers we classify is glass wafers. These are used when a transparent substrate is required and are categorised by a different set of parameters.

The figure below shows Inseto’s nomenclature chart for Glass Wafers:

Glass Wafer Nomenclature Chart
Glass Wafer Nomenclature Chart

The fourth category we use to classify our wafers is SOI wafers or Silicon-on-Insulator.

These wafers are a sandwich of silicon-insulator-silicon. The insulator is typically silicon oxide or sapphire and the make-up of these is highly specific to the end application.

The figure below shows Inseto’s nomenclature chart for SOI Wafers:

Silicon-on-Insulator SOI Wafer Nomenclature Chart
SOI (Silicon-on-Insulator) Wafer Nomenclature Chart

The fifth category we use to classify our wafers is as SOS – Silicon-on-Sapphire.

These wafers have an EPI Silicon layer on Kr grown Sapphire Wafers. The figure below shows Inseto’s nomenclature chart for SOS Wafers:

SOS Wafer Nomenclature
SOS (Silicon-on-Sapphire) Wafer Nomenclature Chart

The final category we use to classify our wafers is Sapphire.

These wafers are prime grade high quality with C, A and R plane crystal orientation from 2″ to 150mm. They are Single or double side polished have low roughness and are defect free.

The figure below shows Inseto’s nomenclature chart for Sapphire Wafers:

Sapphire Wafer Nomenclature
Sapphire Wafer Nomenclature Chart

For more information on our range of Semiconductor Wafer types, please click “HERE“.

Author

Date

Version

Author

Ian Burnett

Date

26 March 2019

Version

IKB044 Rev. 4

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Knowledge Base Fact Sheet

Photolithography Basics

14th December 2019

Introduction to the basics of photolithography (IKB-038).

Photolithography at its most general is the process of patterning the surface of a substrate to build up a complex design or structure.

Photo (UV) Lithography

Photo (or UV) lithography is the technique of pattering through the use of a light sensitive polymer (called photoresist) and a stencil (called a photomask). Through a series of chemical treatments this pattern is inscribed by either etching away of exposed areas or the deposition of new material to fabricate the desired device. For the manufacture of complex devices the number of photolithographic cycles increases.

The first step in any photolithographic process is to prepare the substrate – in most cases the substrate is a silicon wafer but can in theory be any material. Substrate preparation is undertaken to improve the adhesion of the photoresist to the substrate. Typical steps include substrate cleaning – to remove any dirt/contaminates, dehydration bake – to remove any water and then the addition of an adhesion promoter. Going through these steps will reduce the number of contaminates – both organic and inorganic – which will ensure the best results as we move through the lithography process.

Lithography Process
Figure 1.
a) Cleaned and prepared substrate
b) Photoresist spun onto substrate
c) Align to photomask and expose to UV light
d) Develop photoresist.
• Positive removes exposed resist
• Negative removes unexposed resist

Once the substrate has been prepared the photoresist can be applied to the surface. To get the best results a thin uniform coating is required. The thickness of this film is of extreme importance and so the manner in which the resist is dispensed must be precisely controlled. A number of methods have been developed to dispense and coat a substrate with photoresist, the most common deployed of these is spin-coating. A summary of these coating methods can also be found on the Inseto Knowledge base.

In spin-coating the photoresist is deposited onto the substrate and the substrate and resist are then spun on a turntable at 1000s of rpm, spreading out the viscous photoresist into a thin layer. This thin resist is then soft-baked on a hotplate to remove excess solvent and to stabilise the resist film.

The next step in the photolithography process is to align the resist-covered substrate to the photomask and to expose it to UV light. The critical principle in photolithography is that the solubility of the photoresist is changed once exposed to UV light. How this solubility changes defines the type of photoresist – either positive or negative – and the details of the manufacturing process that should be used.

Photoresists come in two categories: positive or negative. In a positive resist, the part of the film that is exposed to the resist becomes more soluble and can be removed with a developer. In a negative the opposite happens, where the resist has been exposed to light the resist becomes harder and can’t be removed by the developer. There are many different compositions and versions of resist, allowing for different heights, temperatures, exposure settings and structures to be manufactured.

When aligning the substrate to the mask we use a mask aligner or a stepper to control where the pattern on the mask is projected onto the substrate below. A mask aligner is a faster process, taking a pattern the same size as the wafer and projecting it onto the wafer. A stepper takes a small pattern and exposes that onto the wafer before moving the substrate a short distance and exposing the same pattern onto a different part of the wafer – replicating the same pattern over and over again.

The crucial aspect of the align and expose step is the exposure of the photoresist with UV light. The UV source can either be a traditional broadband mercury light or the more recent advance using a UV LED array.  The UV source defines the resolution (smallest features) of the lithography process. A rough rule of thumb is that the resolution achievable is slightly more than half the wavelength of light. UV light has a wavelength of ~465nm, so the resolution achieved will be ~250 nm. There are a number of exposure modes available which will also affect the resolution achievable.

Once exposed, the next step is to develop the resist. The developer will wash away either the exposed or unexposed parts of the resist film, depending on the nature of the photoresist. Development is either done as a spray, where a fine mist of developer is sprayed onto the exposed substrate or as a puddle, where a pool of developer is poured onto the exposed substrate. In both cases it will remove the unwanted photoresist leaving the desired pattern.

Now the substrate is ready for the next step of the processing, either the deposition of a thin film onto the surface of the substrate or the etching and removal of the substrate. These techniques can be combined together with multiple iterations of photolithography to make complex designs and patterns.

Other microfabrication techniques similar to lithography such as imprint lithography or electron-beam lithography can also be incorporated into the manufacturing process to produce devices with increasing complexity and functionality.

For further information on our range of equipment for UV Lithography, please click HERE

Author

Date

Version

Author

Chris Valentine

Date

25 October 2019

Version

IKB038 Rev. 2

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Knowledge Base Fact Sheet

Semiconductor Wafer Selection Guide

14th December 2019

A guide to semiconductor wafer selection, explaining the meaning of the various parameters in our wafer nomenclature charts (IKB-046).

Silicon Wafers

Semiconductor wafer selection: Silicon wafers are a thin slice of semiconducting material that is widely used in the production of electronic and micromechanical devices. They are characterised by a number of parameters, which affect their suitability and performance for a chosen task.

1. Wafer diameter

Diameter of the wafer listed in mm. Typically wafers are talked about in inches; typical sizes are 2”,3”,4”,5”,6”,8”& 12” – with 4”,6” and 8” the most commonly used in industry and academia.

2. Type

Type refers to the electrical behaviour of the wafer. Intrinsic (I), behaves as pure silicon. N-type, dominant charge carriers are electrons. P-type, dominant charge carriers are holes. Whether a wafer is P-type or N-type will affect the electrical response of  any device manufactured.

3. Crystallographic Orientation

Wafers are grown as single crystals that have an ordered, regular and repeating structure.  When they are sliced from the ingot the flat surface is aligned along one of several relative directions, known as the orientation. The orientation is classified by Miller indices, typical indices being (100), (110) and (111). Orientation affects the physical properties of the silicon wafer – how it is etched, ion implantation and how it integrates with other materials.

4. Dopant

The dopant is a material that has been deliberately implanted in the silicon to change the TYPE of the silicon. TYPE and DOPANT are linked.

Typical N-type dopants are Phosphorus, Arsenic, and Antimony. These all provide an extra electron to the silicon which is then free to carry current.

Typical P-type dopants are Boron & Gallium. These have one less electron and so leave a ‘hole’ in the silicon lattice which is free to carry current.

5. Growth Method

The growth method refers to the process by which the silicon ingot is grown. There are two main techniques: Czochralski Zone (CZ) and Float Zone (FZ).

CZ: This is the dominant method used to grow commercial silicon wafers due to the better resistance to thermal stress, speed of production and low cost. CZ involves the heating a crucible of polycrystalline silicon until it melts; then dipping a seed of single crystal silicon in and withdrawing slowly to produce an ingot of crystalline silicon.

FZ: This is a high purity alternative to the CZ method. A polycrystalline rod of silicon and a single crystal seed are held face to face and rotated. The rod is then heated by a thin ring and the seed brought in to contact with the tip. The molten silicon orders itself into the single crystal and the heating zone is slowly moved up to extend the ingot of silicon. FZ produces higher purity and higher resistivity Si than is typically possible in CZ processes.

6. Grade

Grade refers to the variety in the quality of the wafers. Typically these are PRIME, TEST and RECLAIMED.

  • Prime are the highest quality and produced to the highest tolerances on flatness, cleanliness and polish
  • Test are similar to prime, except with less rigourous specifications to flatness and cleanliness.
  • Reclaimed are wafers that have been stripped and polished of any previous patterning or processing.

There are sometimes other grades of Si wafer mentioned but these are either synonyms of the above or have a specific tolerance on a certain parameter.

7. Material

The material is the bulk material of the wafer, typically silicon, but this may vary – some transparent substrates such as glass or quartz are needed for optical devices, and more exotic compound materials such as GaAs or InP for specific band gaps.

8. Resistivity

Resistivity is the measure of the resistance to current flow and the movement of the charge carriers (either holes or electrons) through the silicon. Resistivity is measured in Ohm-cm. The dopant level can be adjusted to reach target resistivities, with higher doping lowering the resistivity.

9. Thickness

The thickness of the silicon wafer affects the mechanical properties and is typically expressed in µm (microns) and with a tolerance (± 20µm), The tolerance is measured through a total thickness variation (TTV).

10. Polish

Wafer polishing is the final step in the manufacture of silicon wafers, which allows the production of a smooth, super-flat mirrored surface. There are two options for polishing: single side polish (SSP) and double side polish (DSP)

SSP: Only one face is polished, the second (the backside) is etched.

DSP: Both faces are polished, giving a high flatness to the wafer.

11. Alignment Fiducial

Alignment fiducial refers to the flats or notches used to identify the wafer. Originally flats were used to identify TYPE and well as ORIENTATION, but now there is less convention about what the flats mean, and notches are quite common on 8” (200mm) wafers.

12. Other

At Inseto, we use Other to indicate if the wafers are laser marked with a unique identifier or if they have been stacked in a particular manner.

Silicon Wafers and a guide to the key material selection properties.

Coated Wafers

Semiconductor wafer selection: Coated wafers are a subset of silicon wafers where either one or both surfaces have been coated with an additional material. In the Inseto naming convention they are characterised by COATING – the material the wafer is coated with; and COATING THICKNESS – the thickness of that coating, typically µm, nm or Å.

a. Oxide wafers

One typical coating requested is an Oxide coating. This can be a thermal oxide coating (ATOx) which always coats both sides of the wafer. ATOx stands for atmospheric thermal oxide. Other oxide coating methods include:

Dry Oxide – which produces a thinner oxide layer but with a higher uniformity film.

PECVD Oxide – produces a coating on a single side of the wafer

b. Nitride wafers

A second typical coating requested is a Nitride coating. Silicon Nitride (SiN) offers different mechanical and chemical properties to oxide layers. The nitride can be depositied by PECVD, LPCVD or low stress LPCVD. These variants are changes in the method of deposition and alter the final physical and mechanical properties of the film.

Oxide Coated Silicon Wafers and a guide to the key material selection properties.

Glass Wafers

Glass wafers are generally used where the substrate is required to be transparent. At Inseto we separate out these from silicon and coated silicon wafers as they have some distinct parameters which inform your selection.

1. Wafer diameter

As with Silicon wafers, the diameter is typically listed in mm but may be referred to in inches. 

2. Material

This lists the material the glass is made from, typical options include Borosilicate, Fused Quartz, Fused Silica and Crystal Quartz. Some people use these terms interchangeably or will drop the ‘fused’ and ‘crystal’ terms

3. Crystallographic Orientation

Fused Quartz and Fused Silica have no orientation as they are not crystalline materials. Crystal quartz however does and can be X-Cut, Y-Cut, AT-Cut and ST-Cut depending on how the wafer is removed from the larger crystal.

4. Grade

The grade of the glass wafer listed here refers to the manufacturers specifications. Each has its own specific chemical, mechanical and optical properties.

5. Thickness

As with Silicon wafers this refers to the thickness and tolerance of the wafer, typically listed in µm.

6. Polish

As with Silicon wafers this refers to the finish on the surface of the glass and can be either SSP or DSP. Alongside this there is a rating X/Y, where both X and Y are numbers. X refers to the width of a scratch in µm and Y the diameter of a dig, pit or bubble in hundreths of a mm.

7. Edge Shape

This denotes how the edge of the glass wafer has been shaped. Most commonly a C shape, but chamfered and square cut are also options.

8. Alignment fiducial, Coating type, Coating thickness

The final 3 parameters we list are alignment fiducial, coating type and coating thickness and contain the same information as in the Silicon wafers.

Silica Wafers for Semiconductor Research and a guide to the key material selection properties.

SOI Wafers

The fourth wafer type we separate out is SOI (Silicon on Insulator). SOI wafers make use of a silicon – insulator – silicon substrate and are used for specific applications where reducing parasitic capacitance in the device is crucial. Many photonics devices are also made using SOI wafers to fabricate thin Si optical channels, integrated heaters and other optical devices. They are also used in MEMS production where the thin Si layer is patterned and etched and the underlying insulator layer removed by selective etching to leave a free standing feature. These applications include strain gauges, resonant cantilevers for AFM and molecular scale manipulators as well as microfluidic devices. The choice of insulator within the silicon sandwich is highly specific to the application, but silicon dioxide and sapphire are typical choices for microelectronics and radio frequency applications respectively.  The top layer of silicon is referred to as the ‘device’, the bottom layer the ‘handle’.

There are some standard parameters listed as with silicon wafers – these are Diameter, Type and Crystallographic Orientation. We then list the parameters specific to SOI wafers.

1. Device Thickness

This is the thickness of the top layer of silicon, typically in µm.

2. Growth Method

This is listed twice in an SOI wafer. First is the growth method of the device layer and can be CZ or FZ.

3. Device Resistivity

Measured as with a standard silicon wafer, this is the resistivity of the top layer of silicon in Ohm-cm.

4. BOx

This is the thickness of the insulator layer or ‘buried oxide’ layer, hence BOx.  As with all thicknesses typically µm but can be nm or Å.    

5. Handle Thickness

The thickness of the bottom layer of silicon, typically in µm.

6. Growth Method

This second listing of growth method relates to the handle layer of silicon.

7. Handle Resistivity

Measured as with a standard silicon wafer, this is the resistivity of the bottom layer of silicon in Ohm-cm

8. Backside

This relates to how the backside of the handle layer has been treated and can be a variety of finishes including: Polished, etched, oxide, no oxide and laser marked.

SOI Prime Wafers and a guide to the key material selection properties.

SOS Wafers

Another type of wafer is SOS (Silicon on Sapphire). SOS wafers make use of a silicon layer grown on a sapphire substrate and are a specific subset of SOI wafers, where the insulator is sapphire. SOS wafers are used in applications where the excellent electrical insulation properties of sapphire are required, such as shielding other circuits from stray currents induced by radiation. As these devices are usually fabricated on Undoped FZ-grown Si to utilise the high minority carrier lifetime properties, these wafers are usually made with undoped EPI-grown Si offering similar properties.

At Inseto we use the parameters below to identify the SOS wafers. These are a hybrid of the SOI parameters and the silicon wafer parameters.

1. Diameter

As with the other wafer types this is the diameter of the SOS wafers in mm.

2. Material

This specifies the type of wafer, in the case of all SOS wafers this is SOS – Silicon on Sapphire.

3. Upper Material

The upper material of the SOS wafer, usually this is silicon.

4. Upper Thickness

The thickness of the upper material in microns (µm)   

5. Resistivity

The resistivity of the upper material. This is often critical for SOS-based devices as they are used as the basis of the fabrication for CMOS devices and circuits.

6. Dopant

This indicates if the upper material has been doped and what material has been doped into it. As with Silicon, the dopant is a material that has been deliberately implanted in the silicon to change the type of the silicon.

Typical N-type dopants are Phosphorus, Arsenic, and Antimony. These all provide an extra electron to the silicon which is then free to carry current.

Typical P-type dopants are Boron & Gallium. These have one less electron and so leave a ‘hole’ in the silicon lattice which is free to carry current.

7. Lower Material

The lower material of the SOS wafer, usually this is sapphire.

8. Cut of Lower Material

The cut of the lower material (sapphire wafer) from the original crystal, most common is R- plane as the position of Oxygen atoms in the Sapphire lattice is a good match for (100) Si and the resulting interface is free of defects such as stacking faults and dislocations.

9. Orientation of Plane

This is an additional metric for describing the plane of the lower material (sapphire wafer). For R-plane this is (1102).

10. Lower Material Thickness

The thickness of the lower material in microns (µm).

11. Polish

As with Silicon wafers this refers to the finish on the surface of the glass and can be either SSP or DSP.

12. –

13. Alignment, Coating Type, Coating Thickness and Other

The final 4 parameters we listed are alignment fiducial, coating type, coating thickness and other contain the same information as in the Silicon wafers.

Silicon on Sapphire Wafers

Sapphire Wafers

Sapphire wafers are a thin slice of single crystal sapphire that is widely used in the production of electronic and optical devices. They are characterised by a number of parameters, which affect their suitability and performance for a chosen task.

1. Wafer Diameter

Diameter of the wafer listed in mm. Typically wafers are talked about in inches; typical sizes are 2”,3”,4”,5”,6”,8”& 12” – with 2”,3” and 4” the most commonly used in industry and academia.

2. Growth Method

The growth method refers to the process by which the ingot of single crystal sapphire is produced. For most sapphire wafers this is the Kyropoulos method (abbreviated to Ky or Kr). The Kyropoulos method is a continuation of the Czochralski method (CZ) which is used in the manufacture of silicon wafers. The Kr method allows for the production of very large ingots of single crystal sapphire that can then be processed into wafers.isted twice in an SOI wafer. First is the growth method of the device layer and can be CZ or FZ.

3. Crystal Orientation

Wafers are grown as single crystals that have an ordered, regular and repeating structure.  When they are sliced from the ingot the flat surface is aligned along one of several relative directions, known as the orientation. The orientation is classified by Miller indices as with silicon wafers but more commonly these are referred to by specific planes.

Typical cuts of sapphire are R-plane (1102), C-Plane (0001), A-plane (1120), M-plane (1010) and N-plane (1123). Orientation affects the physical properties of the sapphire wafers – and in particular how it integrates and lattice matches with other materials.

4. Thickness

The thickness of the sapphire wafer affects the mechanical properties and is typically expressed in µm (microns) and with a tolerance (± 20 µm). The tolerance is measured through a total thickness variation (TTV).

5. Polish

Wafer polishing is the final step in the manufacture of silicon wafers, which allows the production of a smooth, super-flat mirrored surface. There are two options for polishing: single side polish (SSP) and double side polish (DSP).

SSP: Only one face is polished, the second (the backside) is etched.
DSP: Both faces are polished, giving a high flatness to the wafer.

6. Alingment Fiducial

Alignment fiducial refers to the flats or notches used to identify the wafer. Originally flats were used to identify TYPE and well as ORIENTATION, but now there is less convention about what the flats mean and notches are quite common on 8” (200mm) wafers.

7. Other

At Inseto, we use Other to indicate if the wafers are laser marked with a unique identifier or if they have been stacked in a particular manner.

150mm Sapphire Wafers

Please visit our wafer store to “order semiconductor wafers online“.

Author

Date

Version

Author

Chris Valentine

Date

24 October 2019

Version

IKB046 Rev. 2

Download

Contents

Category Archives: Lithography

  • Resist Coating Methods

    Resist Coating Methods overviews spin coat, spray coat, inkjet print, dip and slot die coating processes for semiconductor photo resists.

  • Semiconductor Wafer Nomenclature

    This article explains the nomenclature used to identify our semiconductor wafer types and specifications, along with the key descriptive criteria to consider when choosing wafers.

  • What Is A Mask Aligner?

    What is a mask aligner? It is a precision instrument used to transfer a pattern (with micro- / nano-scale features) onto a wafer or substrate during the semiconductor manufacturing process. Read more about all five components here in our Knowledge Base!

  • What Is A Wafer Bonder?

    What is a wafer bonder? A wafer bonder is a precision machine tool used in the fabrication of micro-electrical mechanical systems (MEMS) and other similar technologies. A wafer bonder is used to package together two or more substrates on the wafer-level.

  • What Is Spin Coating?

    What is Spin Coating? This Knowledge Base document overviews the semiconductor fabrication process known as spin-coating, and explains how it works.