Lithography at its most general
is the process of patterning the surface of a substrate to build up a complex
design or structure.
Photo (UV) Lithography
Photo (or UV) lithography is the technique of pattering through the use
of a light sensitive polymer (called photoresist) and a stencil (called a
The first step in any photolithographic process is to prepare the
substrate – in most cases the substrate is a silicon wafer but can in theory be
any material. Substrate preparation is undertaken to improve the adhesion of
the photoresist to the substrate. Typical steps include substrate cleaning – to
remove any dirt/contaminates, dehydration bake – to remove any water and then
the addition of an adhesion promoter. Going through these steps will reduce the
number of contaminates both organic and inorganic which will ensure the best
results as we move through the lithography process.
Once the substrate has been prepared the photoresist can be applied to
the surface. To get the best results a thin uniform coating is required; this
thickness is controlled through a process called spin-coating. The photoresist
is deposited onto the substrate. This is then spun on a turntable to 1000s of
rpm spreading out the viscous photoresist into a thin layer. This thin resist
is then soft-baked on a hotplate to remove excess solvent and to stabilise the
The next step in the photolithography process is to align the resist
covered substrate to the photomask and to expose to UV light. The critical
principle in photolithography is that the solubility of the photoresist is
changed once exposed to UV light. Photoresists come in two categories: positive
In a positive resist, the part of the film that is exposed to the resist
becomes more soluble and can be removed with a developer. In a negative the
opposite happens, where the resist has been exposed to light the resist becomes
harder and can’t be removed by the developer (see Figure 1d). There are many
different compositions and versions of resist, allowing for different heights,
temperatures, exposure settings and structures to be manufactured.
When aligning the substrate to the mask we use a mask aligner or a
stepper to control where the pattern on the mask is projected onto the
substrate below. A mask aligner is a faster process taking a pattern the same
size as the wafer and projecting it onto the wafer. A stepper takes a small
pattern and exposes that onto the wafer before moving the substrate a small way
and exposing the same pattern onto a different part of the wafer – replicating
the same patter over and over again.
The crucial aspect of the align and expose step is the exposure of the
photoresist with UV light. The UV source can either be a traditional broadband
mercury light or the more recent advance using a UV LED array. The UV source defines the resolution
(smallest features) of the lithography process. A rough rule of thumb is that
the resolution achievable is slightly more than half the wavelength of light.
UV light has a wavelength of ~465nm, so the resolution achieved will be ~250
Once exposed the next step is to develop the resist. The developer will
wash away either the exposed or unexposed parts of the resist film depending on
the nature of the photoresist. Development is either done as a spray, where a
fine mist of developer is sprayed onto the exposed substrate or as a puddle,
where a pool of developer is poured onto the exposed substrate. In both cases
it will remove the unwanted photoresist leaving the desired pattern.
Now the substrate is ready for the next step of the processing, either
the deposition of a thin film onto the surface of the substrate or the etching
and removal of the substrate. These techniques can be combined together with
multiple iterations of photolithography to make complex designs and patterns.
Silicon wafers are a thin slice of semiconducting material
that is widely used in the production of electronic and micromechanical devices.
They are characterised by a number of parameters, which affect their
suitability and performance for a chosen tasks.
1. Wafer diameter
Diameter of the wafer listed in
mm. Typically wafers are talked about in inches; typical sizes are
2”,3”,4”,5”,6”,8”& 12” – with
4”,6” and 8” the most commonly used in industry and academia.
Type refers to the electrical
behaviour of the wafer. Intrinsic (I), behaves as pure silicon. N-type,
dominate charge carriers are electrons. P-type, dominate charge carriers are
holes. Whether a wafer is P-type or N-type will affect the electrical response
of any device manufactured.
3. Crystallographic Orientation
Wafers are grown as single
crystals that have an ordered, regular and repeating structure. When they are sliced from the ingot the flat
surface is aligned along one of several relative directions, known as the
orientation. The orientation is classified by Miller indices, typical indices
are (100), (110) and (111). Orientation affects the physical properties of the
silicon wafers – how it is etched, ion implantation and how it integrates with
The dopant is a material that has
been deliberately implanted in the silicon to change the TYPE of the silicon.
TYPE and DOPANT are linked.
Typical N-type dopants are
Phosphorus, Arsenic, and Antimony. These all provide an extra electron to the
silicon which is then free to carry current.
Typical P-type dopants are Boron,
Gallium. These have one less electron and so leave a ‘hole’ in the silicon
lattice which is free to carry current.
5. Growth Method
The growth method refers to the
process by which the silicon ingot is grown. There are two main techniques:
Czochralski Zone (CZ) and Float Zone (FZ).
CZ: This is the dominant method used to grow commercial silicon
wafers due to the better resistance to thermal stress, speed of production and
low cost. CZ involves the heating a crucible of polycrystalline silicon until
it melts; then dipping a seed of single crystal silicon in and withdrawing
slowly to produce an ingot of crystalline silicon.
FZ: This is a high purity alternative to the CZ method. A
polycrystalline rod of silicon and a single crystal seed are held face to face
and rotated. The rod is then heated by a thin ring and the seed brought in to
contact with the tip. The molten silicon orders itself into the single crystal
and the heating zone is slowly moved up and the ingot of silicon extends. FZ
produces high purity and high resistivity Si than typically possible in CZ
Grade refers to the variety in the quality of the
wafers. Typically these are PRIME, TEST and RECLAIMED.
Prime are the highest quality and produced to
the highest tolerances on flatness, cleanliness and polish
Test are similar to prime, except with less
rigourous specifications to flatness and cleanliness.
Reclaimed are wafers that have been stripped
and polished of any previous patterning or processing.
There are sometimes other grades of Si
wafer mentioned but these are either synonyms of the above or have a specific
tolerance on a certain parameter.
The material is the bulk material
of the wafer, typically silicon, but this may vary, some transparent substrates
such as glass or quartz are needed for optical devices and more exotic compound
materials such as GaAs or InP for specific band gaps.
Resistivity is the measure of the
resistance to current flow and the movement of the charge carriers (either
holes or electrons) through the silicon. Resistivity is measured in Ohm-cm. The
dopant level can be adjusted to reach target resistivities, with higher doping
lowering the resistivity.
The thickness of the silicon
wafer affects the mechanical properties and is typically expressed in µm
(microns) and with a tolerance (± ? µm), The tolerance is measured through a
total thickness variation (TTV).
Wafer polishing is the final step
in the manufacture of silicon wafers, which allows the production of a smooth,
super-flat mirrored surface. There are two options for polishing: single side
polish (SSP) and double side polish (DSP)
SSP: Only one face is polished, the second (the backside) is
DSP: Both faces are polished, giving a high flatness to the wafer.
11. Alignment Fiducial
Alignment fiducial refers to the
flats or notches used to identify the wafer. Originally flats were used to
identify TYPE and well as ORIENTATION but now there is less convention about
what the flats mean and notches are quite common on 8” (200mm) wafers.
At Inseto, we use other to
indicate if the wafers are laser marked with a unique identifier or if they
have been stacked in a particular manner.
Coated wafers are a subset of silicon wafers where either one or both surfaces have been coated with an additional material. In the Inseto naming convention they are characterised by COATING – the material the wafer is coated with; and COATING THICKNESS – the thickness of that coating, typically µm, nm or Å.
a. Oxide wafers
One typical coating requested is
an Oxide coating. This can be a thermal oxide coating (ATOx) which always coats
both sides of the wafer. ATOx stands for atmospheric thermal oxide. Other oxide
coating methods include:
Dry Oxide –
which produces a thinner oxide layer but with a higher uniformity film.
PECVD Oxide –
produces a coating on a single side of the wafer
b. Nitride wafers
A second typical coating
requested is a Nitride coating. Silicon Nitride (SiN) offers different
mechanical and chemical properties to oxide layers. The nitride can be
depositied by PECVD, LPCVD or low stress LPCVD. These variants are changes in
the method of deposition and alter the final physical and mechanical properties
of the film.
Glass wafers are generally used where the substrate is required to be transparent. At Inseto we separate out these from silicon and coated silicon wafers as they have some distinct parameters which inform your selection.
1. Wafer diameter
As with Silicon wafers, the
diameter is typically listed in mm but may be referred to in inches.
This lists the material the glass
is made from, typical options include Borosilicate, Fused Quartz, Fused Silica
and Crystal Quartz. Some people use these terms interchangeably or will drop
the ‘fused’ and ‘crystal’ terms
3. Crystallographic Orientation
Fused Quartz and Fused Silica
have no orientation as they are not crystalline materials. Crystal quartz
however does and can be X-Cut, Y-Cut, AT-Cut and ST-Cut depending on how the
wafer is removed from the larger crystal.
The grade of the glass wafer
listed here refers to the manufacturers specifications. Each has its own
specific chemical, mechanical and optical properties.
As with Silicon wafers this
refers to the thickness and tolerance of the wafer, typically listed in µm.
As with Silicon wafers this
refers to the finish on the surface of the glass and can be either SSP or DSP.
Alongside this there is a rating X/Y. where both X and Y are numbers. X refers
to the width of a scratch in µm and Y the diameter of a dig, pit or bubble in
hundreths of a mm.
7. Edge Shape
This denotes how the edge of the
glass wafer has been shaped. Most commonly a C shape, but chamfered and square
cut are also options.
The last wafer type we separate out is SOI (Silicon on
Insulator). SOI wafers make use of a silicon – insulator –silicon substrate and
are used for specific applications where reducing parasitic capacity in the
device is crucial. The choice of insulator within the silicon sandwich is
highly specific to the application but silicon dioxide and sapphire are typical
choices for microelectronics and radio frequency applications
respectively. The top layer of silicon
is referred to as the ‘device’, the bottom layer the ‘handle’.
There are some standard parameters listed as with silicon wafers, these are Diameter, Type and crystallographic orientation. We then list the parameters specific to SOI wafers.
1. Device thickness
This is the thickness of the top
layer of silicon, typically in µm
2. Growth Method
This is listed twice in an SOI
wafer. First is the growth method of the device layer and can be CZ or FZ.
3. Device Resistivity
Measured as with a standard
silicon wafer, this is the resistivity of the top layer of silicon in Ohm-cm
This is the thickness of the
insulator layer or ‘buried oxide’ layer, hence BOx. As with all thicknesses typically µm but can
be nm or Å.
5. Handle Thickness
The thickness of the bottom layer
of silicon, typically in µm.
6. Growth Method
This second listing of growth
method relates to the handle layer of silicon.
7. Handle Resistivity
as with a standard silicon wafer, this is the resistivity of the bottom layer
of silicon in Ohm-cm
This relates to how the backside
of the handle layer has been treated and can be a variety of finishes
including: Polished, etched, oxide, no oxide and laser marked.
With some 90 visitors attending from industry and academia, the inaugural SUSS MicroTec sponsored “UK Lithography Conference”, held on 4th July 2019, had an over-arching theme of ‘productivity and efficiency’ and was a resounding success.
Rutherford Appleton Laboratory, the conference was split into three sessions, the
first of which was entitled ‘Surface Preparation’, which began with sound advice
on substrate selection. For this, Ian Burnett of Inseto, had a clear message: quality
lithography depends heavily on quality wafers. Though SEMI standards exist for
wafer thickness tolerances, flatness, surface roughness etc. for repeat runs,
and to ensure consistent results, there is no substitute for using wafers from
the same ingot, supplied in the order in which they were sliced.
Next in the
session, Joost Driven and Dominique Bouwes of Micronit Mictrotechnologies discussed
material structures, focussing on the benefits of polymer and the associated
challenges of processing it; challenges that include ensuring a crack-free
surface, structural accuracy (i.e. dimensions of features), cleanliness (of
channels, trenches and holes) and adhesion. Figure 1 shows how cracks can form.
Bouwes than gave examples of polymer-based devices; a bio chip for life
sciences and a MEMS-based hair flow sensor.
session concluded with Tim Bruchmueller, Product Manager 200mm coaters, of SUSS
MicroTec discussing recent developments with coating technologies in the SUSS
camp. Using the just-launched SUSS ACS 200 GEN3 LabCluster coater and developer
as an example, and without being overly sales-pitchy, Bruchmueller explained
how, for example, developments around the resist bottle (which is inverted)
reduce the risk of getting air into the dispensers.
Also, by taking advantage of the Peltier-Effect (as exhibited by some semiconductors) means positive or negative temperature differentials can be created for heating or cooling purposes. Where cooling is concerned this means no need for compressors (and their associated vibrations) and refrigerant liquids. Perhaps the biggest benefit is a lower electricity bill, as reflected in figure 2.
for this session was Exposure, and Dr. Marc Hennemeyer, Director of SUSS
MicroTec’s Application Centre for Lithography, started proceedings by giving a
presentation on MEMS processing challenges. These include needing consistent
processing for different types of substrate material (Si, SiO2,
LiTa, ceramics etc.) and the popularity of material stacks (for example,
Si-based CMOS device wafers on top of mechanical device wafers).
relatively large features on substrates with high topographies, large exposure
gaps are caused. However, this can lead to reduced side wall angles. Also,
steppers cannot achieve sufficient process results due to their limited depth
of focus (DOF). In this respect, Dr. Hennemeyer proposed Fresnel Zone Plate
(FZP) processing as a solution, describing FZP as, in essence, a diffractive
lens. The process, which is generally for feature sizes greater than 2um, is somewhat
removed from traditional proximity lithography.
A diagram Dr. Hennemeyer talked around is reproduced here as figure 3. It compares the DOF of a traditional mask used to make a hole versus an FZP.
reference to the above diagram, in the top left we have a round hole in a mask.
To the right, we have a prediction of the light intensity when projected
through the mask. The DOF is relatively close to the mask. Below that, on the
left, we have an FZP mask. The pattern is larger and more complex, requiring
polarity changes in the rings, but the DOF is greater (and further away from
Dr. Hennemeyer held the floor to give a follow-on presentation about improving proximity imaging quality using diffractive elements. A key point made concerned the use of optical proximity correction (OPC) and the inclusion of features on the source mask that are not meant to be printed. Rather they are present to ‘influence’ the shape that will be printed. For example, the rounding effect means that a square in the mask might produce something closer to a circle. However, the presence of features (smaller squares) to ‘re-enforce’ the corners can result in the printing of a much better square; subject to the size of the smaller squares and their distance from the main square on the mask. See figure 4.
on mask aligners is more challenging than on steppers. Simulation provides
considerable benefits though according to Dr. Hennemeyer, who went on to
recount the developments of a joint SUSS/GenISys project. Findings to date
reveal that light source stability and reliable gap settings are key to
implementing OPC, which helps in the creation of ‘sharper’ features and steep
SUSS MicroTec kept the floor for the next presentation, as Christof Kronseder gave an overview of UV LED light sources and recounted a number of developments that have taken place during recent years. The advantages of LED over traditional mercury lamps include lower running costs (during use and by virtue of not requiring a warm-up) and reduced cooling requirements. Kronseder recounted that SUSS began its LED journey with an alternative for 350W mercury lamps and is currently working on a 1kW system.
This session was themed ‘Imprint / Applications’ and began with a presentation from Dr. Simon Drieschner, an Applications Engineer with SUSS MicroTec, on solutions for micro and nano imprinting, using substrate conformal imprint lithography (SCIL) and SUSS’s proprietary SUSS MicroTec imprint lithography equipment (SMILE) respectively (see figure 5).
The presentation included a comparison of stamp materials from a total-cost-of-ownership perspective and factored in curing times, which are often overlooked but essential for volume manufacturing scenarios as they can vary from circa 15 minutes to more than three days. Two main materials were compared, epoxides (which are proven in the field) and hybrid acrylates (which are a relatively new development but watch this space as the benefits are considerable). See figure 6.
concluded with a report from academia, in the form of a presentation from
Swansea University, given by Dominic Chung Man Fung and which provided an
example of the SCIL process as part of an Innovate UK funded project.
was to develop a low cost, volume fabrication process for a wafer scale
distributed feedback (DFB) laser. Challenges included feature size and shape
(plus achieving steep sidewall angles), stamp [soft master] curing time, the
hard master having an anti-stick layer (ASL) and, of course, attaining high
results have been achieved so far on 3” wafers. For instance, an ASL for the
hard master has been created using FDTS (a.k.a. Perfluorodecyltrichlorosilane –
an anti-sticking process used in other technology fields) and soft stamps are
exhibiting high reproducibility. The most impressive achievement however is how
rapidly high yield has been attained – see figure 7.
Future goals include attaining 100% yield (far from unachievable considering the results to date), scaling to 4”, 6” and 8” wafers and performing studies into the lifetime of the soft master.
inaugural UK Lithography Conference concluded with a note of thanks from Matt
Brown of Inseto, the organiser of the event. Thanks went to Rutherford Appleton
Laboratory for hosting the conference, to SUSS MicroTec for their sponsorship
and to the speakers (most of whom had travelled in from outside the UK).
To repeat a
few words from the intro of this report, the event was a resounding
success. The lithography community is facing (and as the conference proved, is
solving) a whole host of technical challenges amidst a backdrop of commercial
Productivity and efficiency are being realised through developments in tools and methodologies and, through networking events like the conference, ideas are being shared and further developed – which is all great news for this exciting industry.